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NXP Semiconductors /LPC408x_7x /UART0 /IIR

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Interpret as IIR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AT_LEAST_ONE_INTERRU)INTSTATUS 0INTID0RESERVED 0FIFOENABLE 0 (ABEOINT)ABEOINT 0 (ABTOINT)ABTOINT 0RESERVED

INTSTATUS=AT_LEAST_ONE_INTERRU

Description

Interrupt ID Register. Identifies which interrupt(s) are pending.

Fields

INTSTATUS

Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].

0 (AT_LEAST_ONE_INTERRU): At least one interrupt is pending.

1 (NO_INTERRUPT_IS_PEND): No interrupt is pending.
INTID

Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).

1 (3_THRE_INTERRUPT): 3 - THRE Interrupt

2 (2A__RECEIVE_DATA_AV): 2a - Receive Data Available (RDA).

3 (1_RECEIVE_LINE_S): 1 - Receive Line Status (RLS).

6 (2B__CHARACTER_TIME_): 2b - Character Time-out Indicator (CTI).
RESERVED

Reserved. Read value is undefined, only zero should be written.
FIFOENABLE

Copies of UnFCR[0].
ABEOINT

End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
ABTOINT

Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data